Design Engineer I Job In Hyderabad at Cadence

Job description:

Cadence is conducting an interview for the submit of Design Engineer I.

BE/BTech with 1-4 years of expertise.
Superb information on SCAN/ATPG/JTAG/MBIST
Expertise with a number of chip tape out that features chip ATE deliver up.
Expertise on gate stage simulation with no timing and timing (SDF) simulations (ATPG/MBIST/JTAG)
Expertise in Check constructions for DFT, IP integration, ATPG fault fashions, check level insertion, protection enchancment methods.
Expertise in scan insertion methods at block stage and chip high stage.
Expertise on Reminiscence BIST era, insertion, verification on RTL/Netlist stage.
Good information and understanding in Analog PHY and Analog Macro assessments.
Good information and understanding on JTAG for IEEE 1149.1/IEEE1149.6 requirements.
Good information on check mode timing constraints
Good information about working block stage and chip STA flows.
Cross area information to resolve DFT points with design, synthesis, bodily design, STA group.
Proficiency in trade normal instruments for scan insertion, ATPG, MBIST and JTAG (preferable Cadence/Tessent instruments)
Expertise with post-silicon deliver up and debug on ATE.
Good information on Perl/Tcl scription abilities
Superb group participant capabilities and wonderful communication abilities to work with a wide range of groups throughout the worldwide group.
Excessive sense of duty and possession throughout the group for profitable tape out and post-silicon deliver up of mission.

Job/Req. ID: R50153

Firm: Cadence

Location: Hyderabad, Telangana

Job Class: VLSI Engineering

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