Chip Structure/Ground Planning Engineer | L&T Semiconductor Applied sciences Job
Job description:
L&T Semiconductor Applied sciences is in search of Chip Structure/Ground Planning Engineer.
Duties and necessities:
This place is for a senior-level bodily design engineer who will work on Ground planning/Bump Planning/ Pin assignments /Feed via/ LFU Optimization/ Work hands-on to resolve important design and execution points associated to bodily verification/implementation and sign-off.
- Sturdy hands-on expertise with Chip Stage / Sub-chip degree flooring planning,
- Performing floor-planning and routing research and implementation at block and full-chip degree
- Push down the top-level floorplan and clock to Partition.
- partition, pin project, Energy planning, IO/Bump Planning, Pad Ring Creation, Die File Creation, RDL Routing, working with Package deal Workforce for Optimize the Bumps.
- Carefully working with Package deal crew and reaching Die file milestones
Job/Req. ID: N/A
Firm: L&T Semiconductor Applied sciences
Location: Bangalore, KA
Job Class: VLSI Engineering
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