ASIC Engineer, Implementation | Meta Job In Bangalore

Job description:

Meta is in search of ASIC Engineers in Bangalore.

The Infra Silicon group at Meta is chargeable for designing and constructing in-house {hardware} accelerator Software-Particular Built-in Circuits (ASICs) to boost Meta’s computing efforts with capability and effectivity at decrease energy and value. The group focuses on creating domain-specific System on Chips (SoCs) that allow Meta’s knowledge facilities to execute computationally-intensive workloads, reminiscent of video transcoding and AI/ML, with increased efficiency and decrease power consumption. They’re organized into a number of key areas, together with structure & algorithms, design & micro-architecture, design verification, implementation & backend design, emulation/prototyping, and system on chip (SoC), which collaborate extensively with different groups to ship complete options for varied technical domains.

Duties:

• Run Logic/Bodily Synthesis utilizing superior optimization methods and generate optimized Gate Degree Netlist for Timing, Space, Energy. Debug the timing/space/congestion points and work with RTL & Bodily designers to resolve them
• Carry out Energy Estimation at RTL and Gate Degree and establish energy discount alternatives
• Run Formal Verification checks between RTL and Gate degree netlist and debug the aborts, inconclusive and Logic Equivalency failures
• Carry out RTL Lint and work with the Designers to create waivers
• Carry out RTL DFT Evaluation and enhance the DFT protection for Caught-at faults
• Carry out Flat and Hierarchical Clock Area Crossing and work with the designers to investigate the advanced clock area crossings and log out the CDC
• Carry out Flat and Hierarchical Reset Area crossing Checks. Perceive the Reset-
• Structure by working with Design and FW groups and develop reset teams and the corresponding reset sequence for RDC
• Develop Timing Constraints for RTL-Synthesis and PrimeTime-STA for the blocks and the top-level together with SOC. Analyze the inter-block timing and give you IO budgets for the varied partition blocks
• Develop Energy Intent Specification in UPF for the multi-Vdd designs
• Growing Automation scripts and Methodology for all FE-tools together with (Lint, CDC, RDC, Synthesis, STA, Energy)
• Work carefully with the Design Engineers, DV Engineers, Emulation Engineers in supporting them with the handoff duties. Work together with Bodily Design Engineers and supply them with timing/congestion suggestions

Minimal {qualifications}:

• Bachelor’s diploma in Laptop Science, Laptop Engineering, related technical subject, or equal sensible expertise
• 2+ years of expertise in Design Integration and Entrance-Finish Implementation
• Expertise with Register-Switch Degree (RTL) Synthesis and design optimization for Energy, Efficiency, Space
• Data of front-end and back-end ASIC instruments. Expertise with RTL design utilizing SystemVerilog or different {Hardware} Description Language (HDL)
• Expertise managing a number of design releases and dealing with cross practical groups to assist and debug timing, space, energy points
• Expertise with Digital Design Automation (EDA) instruments and scripting languages (Python, TCL) used to construct instruments and flows for advanced environments. Expertise with speaking throughout practical inside groups and distributors

Most popular {qualifications}:

• Expertise Data of Register-Switch Degree (RTL) coding utilizing Verilog/System Verilog. Data of Timing/bodily libraries, Static Random Entry Reminiscence (SRAM)
• Expertise with Energy, Efficiency, Space Evaluation and methods for decreasing energy
• Data of Clock Area Crossing, Reset Area Crossing, Logic Error Correction (LEC)
• Scripting and programming expertise utilizing Perl/Python, TCL, and Make
• Data of Low energy design. Expertise with Design Compiler, Spyglass, PrimeTime, Formality or equal instruments
• Synthesis Background, Timing Constraints Improvement, Floorplanning and Static Timing Evaluation (STA)

Job/Req. ID: N/A

Firm: Meta

Location: Bangalore, KA

Job class: VLSI Engineering

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